Addressing of memory matrix

ABSTRACT

In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among n WORD  potentials, while the bit lines are either latched sequentially to potentials selected among n BIT  potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto. This timing sequence is provided with a read cycle during which charges flowing between the selected bit line or bit lines connecting thereto are detected and a “refresh/write cycle” during which the polarization of the cells connecting with selected word and bit lines are brought to correspond with a set of predetermined values.

[0001] The present invention concerns a method of driving a passivematrix addressed display or memory array of cells comprising anelectrically polarizable material exhibiting hysteresis, in particular aferroelectric material, wherein the polarization state of individual,separately selectable cells can be switched to a desired condition byapplication of electric potentials or voltages to word and bit lines insaid matrix

[0002] Particularly the present invention concerns pulsing protocols forthe addressing of individual crossing points in passive matrices usedfor data storage and display purposes. A major concern is the avoidanceof disturbing non-addressed crossing points in the same matrices.Another important concern is to minimize the cumulative signal fromnon-addressed cells in such matrices during reading of stored data.Applications shall typically involve, but are not limited to, matricescontaining a ferroelectric thin film that acts as non-volatile memorymaterial.

[0003] Passive matrix addressing implies the use of two sets of parallelelectrodes that cross each other, typically in orthogonal fashion,creating a matrix of crossing points that can be individually accessedelectrically by selective excitation of the appropriate electrodes fromthe edge of the matrix. Advantages of this arrangement includesimplicity of manufacture and high density of crossing points, providedthe functionality of the matrix device can be achieved via thetwo-terminal connections available at each crossing point. Of particularinterest in the present context are display and memory applicationsinvolving matrices where the electrodes at each crossing point sandwicha material in a capacitor-like structure, henceforth termed a “cell”,and where the material in the cells exhibits polarizability andhysteresis. The latter property confers non-volatility on the devices,i.e. they exhibit a memory effect in the absence of an applied externalfield. By application of a potential difference between the twoelectrodes in a given cell, the material in the cell is subjected to anelectric field which evokes a polarization response, the direction andmagnitude of which may be thus set and left in a desired state,representing e.g. a logic “0” or “1” in a memory application or abrightness level in a display application. Likewise, the polarizationstatus in a given cell may be altered or deduced by renewed applicationof voltages to the two electrodes addressing that cell.

[0004] Examples of passive matrix devices employing ferroelectric memorysubstances can be found in the literature dating back 40-50 years. Thus,W. J. Merz and J. R. Anderson described a barium titanate based memorydevice in 1955 (W. J. Merz and J. R. Anderson, “Ferroelectric storagedevices”, Bell.Lab.Record. 1, pp. 335-342 (1955)), and similar work wasalso reported by others promptly thereafter (see, e.g. C. F. Pulvari“Ferroelectrics and their memory applications”, IRE Transactions CP-3,pp. 3-11(1956), and D. S. Campbell “Barium titanate and its use as amemory store”, J. Brit. IRE 17 (7) pp.385-395 (1957)). An example of apassive matrix addressed display rendered non-volatile by aferroelectric material can be found in US Pat. No. 3,725,899 (W.Greubel) filed in 1970.

[0005] In view of its long history and apparent advantages, it isremarkable that the passive matrix addressing principle in conjunctionwith ferroelectrics has not had a greater impact technologically andcommercially. While important reasons for this may be traced back to thelack of ferroelectric materials that satisfy the full range (technicaland commercial) of minimum requirements for the devices in question, amajor factor has been certain inherent negative attributes of passivematrix addressing. Prominent among these is the problem of disturbingnon-addressed crossing points. The phenomenon is well recognized andextensively discussed in the literature, both for displays and in memoryarrays. Thus, the basics shall not be discussed here, but the reader isreferred to, e.g.: A. Sobel: “Some constraints on the operation ofmatrix displays”, IEEE Trans.Electron Devices (Corresp.) ED-18, p. 797(1971), and L. E. Tannas Jr., “Flat panel displays and CRTs”, pp.106 &seq., (Van Nostrand 1985). Depending on the type of device in question,different criteria for avoiding or reducing disturbance of non-addressedcrossing points can be defined. Generally, it is sought to lower thesensitivity of each cell in the matrix to small-signal disturbances,which can be achieved by cells that exhibit a non-linear voltage-currentresponse, involving e.g. thresholding, rectification and/or variousforms of hysteresis.

[0006] Although general applicability is claimed for the presentinvention, particular focus shall be directed towards ferroelectricmemories, where a thin film of ferroelectric material is stimulated atthe matrix crossing points, exhibiting a hysteresis curve as illustratedgenerically in FIG. 1. Typically, writing of a bit is accomplished byapplying a voltage differential across the film at a crossing point,causing the ferroelectric to polarize or switch polarization. Reading isanalogously achieved by applying a voltage of a given polarization,which either causes the polarization to remain unchanged after removalof the voltage or to flip to the opposite direction. In the former case,a small current will flow in response to the applied voltage, while inthe latter case the polarization change causes a current pulse ofmagnitude larger than a predefined threshold level. A crossing point mayarbitrarily be defined as representing a “0” bit in the former case, a“1” bit in the latter.

[0007] A material with hysteresis curve as shown in FIG. 1 will changeits net polarization direction upon application of a field that exceedsE_(c). However, partial switching shall take place upon application ofvoltages below this value, to an extent depending on the material inquestion. Thus, in a matrix with a large number of crossing points,repeated stimuli of non-addressed crossing points may ultimately degradethe polarization states in the matrix to the point where erroneousreading results. The amount and type of stimulus received bynon-addressed crossing points in a cross-bar passive matrix during writeand read operations depends on how the voltages are managed on alladdressing lines in the matrix during these operations, henceforthtermed the “pulsing protocol”. The choice of pulsing protocol depends ona number of factors, and different schemes have been proposed in theliterature, for applications involving memory materials exhibitinghysteresis. Examples of prior art shall now be given.

[0008] U.S. Pat. No. 2,942,239 (J. P. Eckert, Jr. & al.) desclosespulsing protocols for memory arrays with magnetic cores, each with amagnetic hysteresis curve analogous to the ferroelectric one shown inFIG. 1. Although claiming general applicability for memory elementsexhibiting bistable states of remnant polarization, includingferroelectrics, their invention contains only specific teachings onmagnetic data storage where separate contributions to the total magneticflux in each cell are added or subtracted from several independent linesintersecting in each cell. This is reflected in how cells are linked upin the proffered embodiments, with a readout protocol providingsuperposition of a slow, or “background” biasing stimulus being appliedto all or a subset (e.g. a column or a row) of the cells in the matrix,and with a fast selection pulse being applied between the crossing linescontaining the addressed cell. No teachings are given on efficientvoltage protocols for two-terminal, capacitor-like memory cellscombining high speed, random access to data with restoration of thedestructively read information.

[0009] U.S. Pat. No. 3,002,182 (J. R. Anderson) concerns the problem ofpolarization loss by partial switching of ferroelectric memory cells inpassive matrix addressed arrays of ferroelectric-filled capacitors. Toreduce the partial switching polarization loss during writing, thispatent teaches the use of simultaneous application of addressing pulsesto an addressed row and column such that the former executes anelectrical potential swing of typically +2V_(s)/3 to +3V_(s)/4 (whereV_(s) is the nominal switching voltage) while the latter swings to anegative value sufficient for the potential difference between theelectrodes at the selected crossing point to reach the value V_(s). Withthe remaining columns being switched to a potential in the range+V_(s)/3 to +V_(s)/4, only the selected cell in the matrix is subjectedto a significant switching field, and partial switching at the othercrossing points is strongly reduced (the reduction depends on thematerial properties of the ferroelectric, in particular the shape of thehysteresis curve and the magnitude of the dielectric constant). In analternative pulsing scheme, the same patent teaches the application ofadditional “disturbance compensating pulses” subsequent to each writingoperation, where the selected row is clamped at zero potential while theselected and non-selected columns are pulsed to +V_(s)/4 to +V_(s)/3 and−V_(s)/4 to −V_(s)/3, respectively. The latter operation is claimed toreduce the partial switching induced loss of polarization even further.No physical explanation was provided for this choice of pulsing scheme,however, which appears to rely to a large degree on the inventor'sempirical experience with the ferroelectric materials of his day, inparticular barium titanate. While the basic choice of polarities appearplausible and indeed intuitive to the person skilled in the art offerroelectrics, the description given is insufficient to provide anadequate guide to selection of pulse magnitudes and timing in concreteterms for generalized cases. For reading out the stored information orclearing the cells before a writing operation, the inventor proposes theapplication of the full switching voltage −V_(s) to the selected row orrows, referring to “a manner well known in the art”. Selection of thecolumn electrode voltages is treated in a nebulous fashion. It mayappear that the selected column electrode is clamped at ground, with allnon-selected column electrodes biased to −V_(s)/3 or −V_(s)/4 (cf. FIG.4B in U.S. Pat. No. 3,002,182). However, this leads to a voltage load of2V_(s)/3 to 3V_(s)/4 on the non-selected cells in the same row as theselected cell, with obvious danger of partial switching. Thus, it wouldat best seem that the invention shall be poorly suited for situationswhere a large number of read operations are involved between each write,and the general applicability to realistic ferroelectric devices appearsdoubtful.

[0010] U.S. Pat. No. 3,859,642 (J. Mar) discloses a memory concept basedon a passive matrix addressing scheme, where an array of capacitors withprogrammable bistable capacitance values is subjected to a two-levelexcitation during the reading cycle. The memory function resides in thebistability of the capacitors, which are assumed to be of themetal-insulator-semiconductor (MIS) type or equivalent, exhibiting ahysteresis loop which is centered around an offset voltage and wellremoved from the zero offset point. Writing of data is achieved bybiasing the row and column lines crossing at the selected capacitor topolarities +V and −V, respectively, alternatively to −V and +V,respectively, depending on which of the two bistable states is to bewritten. The resulting net bias is thus +−2V on the selected capacitor,and does not exceed an absolute magnitude V on non-selected capacitors,where V is defined as being below threshold for writing. Partial writingis apparently not considered to be a problem, and no particularprovisions are described in that connection beyond the simple schemereferred here. Thus, the teachings of U.S. Pat. No. 3,859,642 cannot beseen as having any prior art significance relative to the subject matterof the present invention.

[0011] A one-third selection scheme for addressing a ferroelectricmatrix arrangement is disclosed in U.S. Pat. No. 4,169,258 (L. E.Tannas, Jr.). In this case, the x- and y lines in a passive matrixaddressing arrangement are subjected to a pulsing protocol where(unipolar) voltages with relative magnitudes 0, ⅓, ⅔ and 1 are appliedin a coordinated fashion to all x and y lines. Here, voltage value 1 isthe nominal voltage amplitude employed for driving a given cell from alogic state “OFF” to “ON”, or vice versa, with the typical coercivevoltage being exemplified as a value between ½ and ⅔. An importantlimitation of the scheme taught in the patent is that the pulseprotocols are predicated upon all cells starting out with the sameinitial polarization magnitude and direction (“OFF”), i.e. the wholematrix must be blanked to an “OFF” state before a new pattern of statescan be written into the matrix cells. Furthermore, any “ON” state on thesame y-line as the addressed cell shall receive a disturb pulse ofmagnitude ⅔ in the direction of the “OFF” state, leading to partialswitching in most known ferroelectrics. While these limitations may beacceptable in certain types of displays and memories, this is not thecase in the vast majority of applications.

[0012] Total blanking is not subsumed under what Tannas Jr. terms theconventional method “one-half selection scheme”, which is described indetail in the cited U.S. Pat. No. 4,169,258. However, the latter schemeexposes the non-selected cells to disturbing pulses of relative value ½.This is generally deemed unacceptable for all practical memoryapplications employing traditional ferroelectric materials such asinorganic ceramics. Furthermore, the one-half selection scheme is onlydescribed in terms of single switching events in the addressed cells,which destroy the pre-switching polarization states.

[0013] Thus, in memory and display applications where it is desired tobe able to change the logic content of individual cells withoutdisturbing other cells or having to blank and reset the whole device,there is a clear need for improvement over the existing prior art.

[0014] Hence it is a major object of the invention to describe voltagevs. time protocols for driving the x and y passive matrix addressinglines in nonvolatile memories exhibiting ferroelectric-like hysteresiscurves so as to minimize disturbance of non-selected memory cells duringwriting as well as reading of data to/from said memories. It is afurther object of the invention to describe voltage protocols thatreduce charging/discharging transients and thus to achieve high speed.It is a further object of the invention to describe voltage protocolsthat permit simple, reliable and cheap electronic circuitry to performdrive and sense operations on the memory matrices.

[0015] The above objects as well as other advantages and features areachieved with a method according to the invention which is characterizedby controlling individually a potential on selected word and bit linesto approach or coincide with one of n predefined potential levels, wheren≧3, the potentials on said selected word and bit lines forming subsetsof said n potentials involving n_(WORD) and n_(BIT) potentials,respectively; controlling the potentials on all word- and bit lines in atime-coordinated fashion according to a protocol or timing sequence,whereby word lines are latched in a predetermined sequence to potentialsselected among the n_(WORD) potentials, while bit lines are eitherlatched in a predetermined sequence to potentials selected among then_(BIT) potentials or they are during a certain period of the timingsequence connected to circuitry that senses the charges flowing betweenthe bit line(s) and the cells connecting to said bit line(s); arrangingsaid timing sequence to encompass at least two distinct parts, includinga “read cycle” where charges flowing between said selected bit line(s)and the cells connecting to said bit line(s) are sensed, and a“refresh/write cycle” where polarization state(s) in cells connectingwith selected word- and bit lines are brought to correspond with a setof predetermined values.

[0016] According to the invention it is advantageous allowing one ormore bit lines to float in response to charges flowing between the bitline and the cells connecting to said bit line during said read cycle,and clamping all voltages on the word and bit lines during therefresh/write cycle.

[0017] In a first advantageous embodiment of the invention the valuesn=3, n_(WORD)=3, and n_(BIT)=3 are selected in case the voltages acrossnon-addressed cells do not significantly exceed V_(S)/2, where V_(S) isthe voltage across the addressed cell during read, refresh and writecycles.

[0018] In a second advantageous embodiment of the invention the valuesn=4, n_(WORD)=4, and n_(BIT)=4 are selected in case the voltages acrossnon-addressed cells do not significantly exceed V_(S)/3, where V_(S) isthe voltage across the addressed cell during read, refresh and writecycles.

[0019] In a third advantageous embodiment of the invention the valuesn=5, n_(WORD)=3, and n_(BIT)=3 are selected in case the voltages acrossnon-addressed cells do not significantly exceed V_(S)/3, where V_(S) isthe voltage across the addressed cell during read, refresh and writecycles.

[0020] It is according to the invention preferred to subjectnon-addressed cells along an active word line and along active bitline(s) to a maximum voltage during the read/write cycle that deviatesby a controlled value from the exact values V_(S)/2 or V_(S)/3, and itis then preferable subjecting non-addressed cells along an active wordline to a voltage of a magnitude that exceeds the exact values V_(S)/2or V_(S)/3 by a controlled voltage increment, and at the same timesubjecting non-addressed cells along selected active bit lines to avoltage of a magnitude that is less than the exact values V_(S)/2 orV_(S)/3 by a controlled voltage decrement, the controlled voltageincrement and voltage decrement preferably being equal to each other.

[0021] It is according to the invention advantageous adding a controlledvoltage increment δ₁ to the potentials Φ_(inactive)WL of inactive wordlines and adding a controlled voltage increment δ₂ to the potentialsΦ_(inactive)BL of inactive bit lines, where δ₁=δ₂=0 corresponds to theread/write protocols with maximum V_(S)/2 or V_(S)/3 voltage exposure onnon-selected cells. In this connection is preferably δ₁=δ₂≠0.

[0022] It is according to the invention considered advantageouscontrolling a quiescent potential (the potential imposed on the word andbit lines during the time between each time the read/refresh/write cycleprotocol is employed) to have the same value on all word and bit lines,i.e. a zero voltage is imposed on all cells. Further it is according tothe invention considered advantageous selecting the quiescent potentialson one or more of the word and bit lines among one of the following: a)System ground, b) Addressed word line at initiation of pulsing protocol,c) Addressed bit line at initiation of pulsing protocol, d) Power supplyvoltage. It is also according to the invention considered advantageousselecting the potential on the selected bit line(s) in a quiescent statesuch that it differs from that at the onset of a floating period (readcycle), and bringing said potential from a quiescent value to that atthe onset of the floating period, where it is clamped for a period oftime comparable to or exceeding a time constant for charging the bitline (“pre-charge pulse”). According to the invention it is consideredadvantageous preceding the read cycle with a voltage shift on inactiveword lines, whereby the non-addressed cells on an active bit line aresubjected to a voltage bias equal to that occurring due to the activebit line voltage shift during the read cycle, said voltage shift on theinactive word lines starting at a selected time preceding said voltageshift on the active bit line, and terminating at the time when thelatter voltage shift is initiated, in such a way that a perceivedvoltage bias on said non-addressed cells on the active bit line iscontinuously applied from the time of initiation of said voltage shifton the inactive word lines and up to the time of termination of saidvoltage shift on the active bit lines (“pre-charge pulse”).

[0023] Finally it is according to the invention considered advantageousapplying a pre-read reference cycle which precedes the read cycle and isseparated from it by a selected time, and which mimics precisely thepulse protocol and current detection of said read cycle, with theexception that no voltage shift is imposed on an active word line duringsaid pre-read reference cycle, and employing a signal recorded duringsaid pre-read reference cycle as input data to the circuitry thatdetermines the logic state of the addressed cell, in which case saidsignal recorded during the pre-read cycle may be subtracted from asignal recording during the read cycle.

[0024] An essential aspect of the present invention is to control thetime-dependent voltages on all the x and y lines in the matrix in acoordinated fashion according to one of the protocols describedhereunder. These protocols ensure that no non-addressed cell (crossingpoint) in the matrix experiences an interline voltage exceeding apredetermined value which is well below a level at which disturbance orpartial switching occurs. The basic principles of the invention andexemplary embodiments shall now be described below and with reference tothe appended drawing figures, wherein

[0025]FIG. 1 shows a principle drawing of a hysteresis curve for aferroelectric memory material,

[0026]FIG. 2 a principle drawing of a passive matrix addressingarrangement with crossing electrode lines, and cells containing aferroelectric material localized between these electrodes where theyoverlap.

[0027]FIG. 3 the sum of voltage steps around a closed loop in thematrix,

[0028]FIG. 4 a read and write voltage protocol requiring three separatevoltage levels to be controlled on the word- and bit lines,

[0029]FIG. 5 an alternative variant of the three level voltage protocolin FIG. 4,

[0030]FIG. 6 a read and write voltage protocol requiring four separatevoltage levels to be controlled on the word- and bit lines,

[0031]FIG. 7 an alternative variant of the four level voltage protocolin FIG. 6,

[0032]FIG. 8 a read and write voltage protocol requiring five separatevoltage levels to be controlled on the word- and bit lines,

[0033]FIG. 9 an alternative variant of the five level voltage protocolin FIG. 8,

[0034] FIGS. 10-13 alternative voltage protocols to those shown in FIGS.6-9, the difference being that pre-charging pulses on inactive wordlines are now included,

[0035]FIG. 14 an example of a read and write protocol involving apre-read reference cycle, and

[0036]FIG. 15 a readout scheme based on full row parallel detection.

[0037] The general background and the basic principles of the presentinvention shall now be discussed in some detail.

[0038] It is understood that the materials constituting the memoryfunction in displays and memory devices as per the instant inventionexhibit hysteresis as exemplified in a generic fashion in FIG. 1.Relevant materials are electrets, ferroelectrics or a combination of thetwo. For simplicity, it shall be assumed in the following that thematerial in question is a ferroelectric, but this shall not restrict thegenerality of the present invention.

[0039] As a consequence of prior exposure to electric fields, thematerial is assumed to reside in one of two polarization states when inzero external field, represented by the points +PR and −PR in FIG. 1.Application of a voltage across the cell containing the ferroelectriccauses the latter to change its polarization state, tracing thehysteresis curve in a manner well known to the person skilled in the artof ferroelectrics. For convenience, the hysteresis curve in FIG. 1 isshown with the voltage rather than the field along the abscissa axis.

[0040] Below shall be described how, in a passive matrix configuration,voltages can be applied to the crossing word- and bit lines in such afashion that a single, freely chosen cell in the matrix experiences apotential difference V_(S) between the two electrodes crossing at thatpoint which has sufficient magnitude to cause the ferroelectric toswitch its polarization direction in either positive or negativedirection (depending on the polarity of the applied field between theelectrodes) and ending up at one of the points +P_(R) or −P_(R) on thehysteresis curve after removal of the externally imposed field. At thesame time, no other cell in the matrix shall be subjected to a potentialdifference that causes an unacceptable (according to prior definedcriteria) change in the polarization state. This is ensured by thepotential difference across non-addressed cells (the “disturbingvoltage”) never exceeding +V_(S)/n, where n is an integer or non-integernumber of typical value of 2 or more.

[0041] Depending on the required switching speed, etc, the nominalswitching voltage V_(S) employed for driving the polarization state ofthe ferroelectric is typically selected considerably larger than thecoercive voltage V_(C) (cf. FIG. 1). However, it cannot be chosenarbitrarily large, since the pulsing protocols described here shall onlyreduce the disturbing voltage to a certain fraction (typically ⅓) ofV_(S), which level should be less than V_(C).

[0042] Before proceeding to a discussion of specific pulsing protocols,it may be useful to review the problem in a generalized fashion, withreference to the matrix shown in FIG. 2. For easy reference and toconform with standard usage, it is henceforth referred to the horizontal(row) and vertical (column) lines as “word lines” (abbreviated: WL) and“bit lines” (abbreviated: BL), respectively, as indicated in the figure.It is desired to apply a voltage that is sufficiently high to switch agiven cell, either for defining a given polarization direction in thatcell (writing), or for monitoring the discharge response (reading).Accordingly, the cell is selected by setting the potentials of theassociated word and bit lines (the “active” lines) such that:

Φ_(activeBL)−Φ_(activeWL) =V _(S).  (1)

[0043] At the same time, the numerous word- and bit lines that cross atnon-addressed cells must be controlled in potential such that thedisturbing voltages at these cells are kept below the threshold forpartial switching. Each of these “inactive” word- and bit lines crossthe active bit- and word line at a non-addressed cell. Referring to FIG.2, one notes that four distinct classes of cells can be defined in thematrix, according to the perceived voltages across the cells:

[0044] i) V_(i)=Φ_(activeBL)−Φ_(activeWL): Active word line crossingactive bit line (the selected cell)

[0045] ii) V_(ii)=Φ_(inactiveBL)−Φ_(activeWL): Active word line crossinginactive bit line,

[0046] iii) V_(iii)=Φ_(activeBL)−Φ_(inactiveWL): Inactive word linecrossing active bit line,

[0047] iv) V_(iv)=Φ_(inactiveBL)−Φ_(inactiveWL): Inactive word linecrossing inactive bit line.

[0048] In practical devices where it is desired to minimize cost andcomplexity, it is of primary interest to focus on the special case whereall inactive word lines are at a common potential Φ_(inactiveWL), andcorrespondingly all inactive bit lines are at a common potentialΦ_(inactiveBL). By summing voltages around a closed loop in the matrixgrid as shown in FIG. 3, the following condition applies:

V _(i) =V _(ii) +V _(iii) −V _(iv).  (2)

[0049] Given the value of V_(i)=V_(S), the minimum voltage valueattainable across the non-addressed cells is thus:

|V _(ii) |=|V _(iii) |=|V _(iv) |=V _(S)/3.  (3)

[0050] To achieve this, at least four separate potentials (i.e. Φ₀,Φ₀+V_(S)/3, Φ₀+2V_(S)/3, Φ₀+V_(S); where Φ₀ is a reference potential)must be imposed on the electrodes in the matrix, and any change inpotential on one of the electrodes must be coordinated with adjustmentsin the other potentials such that no cell experiences a voltageexceeding V_(S)/3. In practice, several other factors must be heededalso, e.g. related to minimizing switching transients (charge/dischargecurrents) and reducing the complexity of the driving circuitry,resulting in pulsing protocols such as those described below. Oneexample is an overall shift in potentials by adding or subtracting thesame voltage to all four levels.

EXAMPLE 1 Three-level (V_(S)/2) Switching Protocol

[0051] In certain special cases, a simplified pulsing protocol may beused, where all inactive word and bit lines are given the samepotential, i.e. V_(iv)=0. In that case, the minimum voltage valueattainable across non-addressed cells becomes:

V _(ii) =V _(iii) =V _(S)/2  (4)

[0052] and at least three separate potentials are needed for managingthe write and read operations (i.e. Φ₀, Φ₀+V_(S)/2, Φ₀+V_(S); where Φ₀is a reference potential).

[0053] As was mentioned above, partial switching may represent a seriousproblem at voltage levels of V_(S)/2, rendering three-level protocolsunacceptable. However, the degree of partial switching at a givenapplied voltage depends explicitly on the ferroelectric material inquestion. Referring to FIG. 1, materials with a square shaped hysteresiscurves shall in many applications yield acceptable performance.

[0054] Recently, certain classes of ferroelectrics such as organicpolymers have received much attention as memory substances in advanceddata storage concepts. In addition to other attractive features, thesesmaterials exhibit hysteresis curves far more square shaped than those ofthe ceramic ferroelectrics that have traditionally dominateddevelopments in the field of ferroelectric-based non-volatile memorydevices. Thus, it has become relevant to define pulsing protocols whichcan satisfy the requirements of realistic and optimized electronicdevice designs. Following upon the partial switching problems thatdiscouraged development and exploitation of early efforts based onthree-level switching protocols, these aspects have received very littleattention, which the present invention sets out to remedy.

[0055] Now examples of preferred embodiments shall be given.

[0056]FIGS. 4 and 5 illustrate some three-level pulsing protocolsaccording to the present invention, comprising a complete read cycle anda refresh/write cycle. Only the pulse diagrams for the active word- andbit lines are shown. The inactive word lines may be kept stable atV_(S)/2 throughout the read/write cycle, as may the inactive bit lines.Alternatively, the latter may during the read cycle each be connectedwith a separate sense amplifier, which would be biased near the bit linevoltage when the bit line clamp is released (full row readout). In thediagrams shown in FIGS. 4 and 5, the time markers are as follows:

[0057] t₀: Word line latched, active pulldown to 0 (FIG. 4) or pullup toV_(S) (FIG. 5)

[0058] t₁: Bit line clamp released—sense amplifier ON

[0059] t₂: Bit line decision—data latched

[0060] t₃: Word line returned to quiescent V_(S)/2

[0061] t₄: Write data latched on bit lines

[0062] t₅: Word line pulled to V_(S) (FIG. 4) or zero (FIG. 5)—set/resetcapacitors

[0063] t₆: Word line returned to quiescent V_(S)/2

[0064] t₇: Bit lines actively returned to V_(S) (FIG. 4) or zero (FIG.5) clamp

[0065] t₈: Read/write cycle complete

[0066] The read cycle investigates the state of the polarization of theaddressed cell. Depending on the polarization direction, the readoperation may leave the polarization unchanged, or it may reverse thepolarization direction (destructive read). In the latter case, theinformation must be refreshed if it is desired avoid loss of storeddata. This implies that the polarization must be driven in the oppositedirection of the read operation in an appropriate cell (not necessarilythe one that was read) somewhere in the matrix. This is achieved by thepart of the protocol dedicated to refresh/write, as shown. The twobranches in the bit line voltage protocol correspond to the cases wherethe polarization is left unchanged and reversed, respectively. Anisolated write operation is trivially achieved by omitting the precedingread operation.

[0067] As shown in FIGS. 4 and 5, it is clear that non-addressed cellsshall not receive voltages exceeding ½ of the nominal switching voltage,neither during reading or refresh/writing periods. In addition, onenotes that there are included event delays in the pulsing sequence tofacilitate transient ringdown and latching of data. Depending on how thememory device is to be operated, the bit line potential in the quiescentstate (i.e. between read/refresh/write cycles) may be chosen to matchthat of the bit line at the start of the read cycle (cf. FIGS. 4 and 5)or it may match the quiescent potential of the word line (not shownhere). In the former case, appropriate when cycling is intense and athigh speed, charging currents at the start of the read cycle areminimized. In the latter case, long-term effects of an imposed field inthe cells (e.g. imprint) are avoided.

[0068] It should be clear that the examples shown in FIGS. 4 and 5 maybe modified (e.g. by concurrent shifting of all potentials, or by minordepartures from exact voltage levels in the three-level scheme shown)without departing from the essential principles illustrated therein.

EXAMPLE 2 Four-level (V_(S)/3) Switching Protocol

[0069] As described above, by employing at least 4 different potentiallevels on the word and bit lines, one can ensure that no non-addressedcell experiences a voltage exceeding ⅓ of the nominal switching voltage.FIGS. 6 and 7 illustrate two variants of a preferred scheme for readingas well as refreshing/writing data, according to the present invention.Here, the time markers are as follows:

[0070] t₀: Quiescent state; all word- and bit lines at 2V_(S)/3 (FIG. 6)or V_(S)/3 (FIG. 7)

[0071] t₁: Inactive bit lines adjusted from quiescent value to V_(S)/3(FIG. 6) or 2V_(S)/3 (FIG. 7)

[0072] t₂: Addressed bit line(s) adjusted to V_(S) (FIG. 6) or 0 (FIG.7). Time delay from t₁ to t₂ is arbitrary; zero or negative timings areacceptable also

[0073] t₃: After a programmable read-set up delay, the addressed wordline is adjusted from quiescent potential to 0 V (FIG. 6) or V_(S) (FIG.7), a voltage of magnitude V_(S) between addressed word and bit lines.Unaddressed word lines remain at 2V_(S)/3 (FIG. 6) or V_(S)/3 (FIG. 7)

[0074] t₄: Addressed word line returned to quiescent potential afterread delay

[0075] t₅: All bit lines returned to quiescent potential

[0076] t₆: Read cycle now complete. All word- and bit lines in quiescentstate (2V_(S)/3 in FIG. 6; V_(S)/3 in FIG. 7)

[0077] t₇: All inactive word lines adjusted from quiescent to V_(S)/3(FIG. 6) or 2V_(S)/3 (FIG. 7)

[0078] t₈: Addressed bit line(s) to be written to logic state “1” areadjusted to 0 V or are left at quiescent potential to remain in logic“0”. (FIG. 6) Addressed bit line(s) to be written to logic state “0” areadjusted to V_(S) or are left at quiescent potential to remain in logic“1” (FIG. 7)

[0079] t₉: Addressed word line is adjusted to V_(S) (FIG. 6) or 0 (FIG.7), introducing a voltage of magnitude V_(S) across addressed cell(s)

[0080] t₁₀: Addressed bit line(s) returned to quiescent 2V_(S)/3 (FIG.6) or V_(S)/3 (FIG. 7) after write delay

[0081] t₁₁: All word lines returned to quiescent potential

[0082] t₁₂: Write cycle complete. All word- and bit lines in quiescent.

[0083] Apart from the increased voltage level complexity, the basicfeatures are similar to those referred above in connection with thethree level schemes. Now, however, no non-addressed cell is exposed to avoltage exceeding V_(S)/3 in the course of a complete read/write cycle,which shall cause only minor partial switching in most ferroelectricmaterials of relevance here. Again, several variants on a common themeare possible. Thus, FIGS. 6 and 7 show a return to zero applied voltageacross all cells in the quiescent state (cf. the above discussion underthe three-level switching protocol), which corresponds to word and bitline potentials of 2V_(S)/3 or V_(S)/3, whereas other potential levelson the word- and bit lines are possible in the quiescent state thateither yield zero voltages across the cells or voltages of absolutevalue ≦|V_(S)|/3. Such variants shall be assumed obvious to the skilledperson and shall not be pursued in further detail here.

[0084] The timing diagrams in FIGS. 6 and 7 are equivalent in principle,one being an “inverted” version of the other, In practice, however, onemay be preferred over the other. Thus, the scheme shown in FIG. 6implies a voltage at the sense amplifier input during the read cyclenear V_(S). In the scheme of FIG. 7, however, the voltage is near zero.This may permit the use of low voltage components with a single highvoltage pass transistor per bit line.

EXAMPLE 3 Five-level (V_(S)/3) Switching Protocol

[0085] A class of seemingly more complex, but in certain respects moresimply implemented pulsing protocols involve the application of fivedifferent potential levels to the word- and bit lines during a completeread/write cycle. Explicit examples of two preferred embodiments areshown in FIGS. 8 and 9. The time markers are as follows:

[0086] t₀: Quiescent state: all word- and bit lines at 2V_(S)/3 (FIG. 6)or V_(S)/3 (FIG. 7)

[0087] t₁: Inactive bit lines adjusted from quiescent value to V_(S)/3(FIG. 6) or 2V_(S)/3 (FIG. 7)

[0088] t₂: Addressed bit line(s) adjusted to V_(S) (FIG. 6) or 0 (FIG.7). Time delay from t₁ to t₂ is arbitrary; zero or negative timings areacceptable also

[0089] t₃: After a programmable read-set up delay, the addressed wordline is adjusted from quiescent potential to 0 V (FIG. 6) or V_(S) (FIG.7), inducing a voltage of magnitude V_(S) between addressed word and bitlines. Unaddressed word lines remain at 2V_(S)/3 (FIG. 6) or V_(S)/3(FIG. 7)

[0090] t₄: Addressed word line returned to quiescent potential afterread delay

[0091] t₅: All bit lines returned to quiescent potential

[0092] t₆: Read cycle now complete, All word and bit lines in quiescentstate (2V_(S)/3 in FIG. 6; V_(S)/3 in FIG. 7)

[0093] t₇: Inactive bit lines adjusted from quiescent to V_(S) (FIG. 8)or V_(S)/3 (FIG. 9)

[0094] t₈: Addressed bit line(s) to be written to the “1” state areadjusted to V_(S)/3, (FIG. 8) while those that shall remain in state “0”are adjusted to V_(S) addressed bit line(s) to be written to the “0”state are adjusted to V_(S)/3, while those that shall remain in state“1” are adjusted to V_(S) (FIG. 9)

[0095] t₉: Addressed word line is adjusted to 4V_(S)/3 (FIG. 8) or 0(FIG. 9), introducing a voltage of magnitude V_(S) across addressedcell(s). Non-addressed word lines remain at 2V_(S)/3

[0096] t₁₀: Addressed word lines returned to quiescent potential afterwrite delay

[0097] t₁₁: All bit lines returned to quiescent potential

[0098] t₁₂: Write cycle complete. All word and bit lines in quiescent.

[0099] Here, a fifth voltage level, V_(CC), is involved. It is typicallyof magnitude 4V_(S)/3, and is applied to the active word line during thereading (FIG. 8) or refresh/write (FIG. 9) cycle. One notes that whilethe four-level schemes in FIGS. 6 and 7 require all word- and bit linesto be driven at four levels in the course of the complete read/writecycle, the five-level schemes in FIGS. 8 and 9 require only threeseparate voltage levels to be applied to the word lines and threeseparate but not identical voltage levels to be applied to the bitlines. This provides opportunities for optimization and simplificationof the driving and sensing electronics supporting the device. Furthersimplification can be realized by choosing 4V_(S)/3=V_(CC) close to thepower supply voltage.

EXAMPLE 4 Switching Protocols Involving Pre-charging of Non-addressedCells on Active Bit Lines

[0100] So far, primary focus has been on avoiding partial switching ofnon-addressed cells. However, it is also desirable to design switchingprotocols that simultaneously minimize the effect of parasitic currentflows within the memory matrix during the read cycle:

[0101] In memory matrices based on passive matrix addressing, the areadata storage density is maximized by using matrices that are as large aspossible. This implies that each matrix should contain the largestpossible number of crossing points between word- and bit lines, and anygiven bit line must consequently cross a large number of word lines.When a given word and bit line crossing is selected, the large number ofnon-selected crossing points between the bit line and all of thenon-selected crossing word lines constitute a correspondingly largenumber of parasitic current leakage paths (capacitive, inductive, ohmic)which may add up to slow down the device and reduce the contrast ratioof as-read logic “1”s and “0”s.

[0102] One method of reducing the effect of parasitic currents on thedetermination of logic states is to pre-charge the non-addressed cellson the active bit line to a level corresponding to that which would beapproached during the reading of the active cell. This procedure isimplicit in the voltage protocols shown in FIGS. 6-9. At time point 2,i.e. prior to applying the read voltage step to the active word line (attime point 3 in the figures) the active bit line voltage is shifted toits read cycle value, creating a voltage bias between the active bitline and all word lines. This initiates the spurious current flows inall the non-active cells on the active bit line. These currents aretypically transient, reflecting polarization phenomena in the cells, anddie out or are greatly diminished after a short time. Thus, by makingthe time gap between time points 2 and 3 sufficiently long, the spuriouscurrent contributions to the switching currents sensed during thereading cycle are greatly diminished. Certain limitations adhere to thisscheme: If the time gap between time points 2 and 3 becomes very long,it has obvious implications on the data access speed and overall readcycle time. Additionally, the cumulative effect of repeated cycling withlong pre-charging times may be to cause partial switching and imprint,which was sought avoided by having zero voltage across all cells in thequiescent state.

[0103] The voltage protocol diagrams in FIGS. 6-13 do not show the senseamplifier timing, which may vary from case to case, depending upon thedynamics of the polarization switching and spurious current response inthe addressed and in the non-addressed cells. The sense amplifiers mustbe activated after time point 2 to avoid the spurious current transientfrom the non-addressed cells, and not much later than time point 3 inorder to capture any polarization reversal current in active cells thatare switched by the read cycle.

[0104] One notes that by advancing the time point 2 well ahead of timepoint 3, not only the inactive cells on the active bit line aresubjected to an early voltage bias of magnitude |V_(S)/3|, but also theactive cell. Thus, some of the switching charge in the active cell isdrained away before the sense amplifier has been connected. Themagnitude of this effect, which is undesirable since it reduces the readsignal, depends on the polarization characteristics of the memorymaterial in the cells and may range from negligible to significant. Inthe latter case, one may implement a slight modification of the voltageprotocol by introducing a voltage shift on the inactive word lines asillustrated in FIGS. 10-13. The leading edge of the shift occurs at timepoint 0, and the trailing edge coincides with the leading edge of theactive bit line voltage shift at time point 2. By precisely controllingthe trailing and leading edge shifts at time point 2, the voltage acrossthe non-addressed cells on the active bit line shall rise from zero to amagnitude |V_(S)/3| at time point 0 and remain unchanged at this valueuntil time point 5, i.e. after completion of the read cycle. The timepoint 2 may now be optimized for the readout process in the active cell,without limitations relating to driving the pre-charge transient in thenon-addressed cells. As can be seen from FIGS. 10-13, the voltage acrossnon-addressed cells is always maintained at less than a magnitude|V_(S)/3| in these modified schemes, but 4 voltage levels are nowinvolved on the word lines in the five-level protocols, compared tothree levels previously.

EXAMPLE 5 Switching Protocols Involving a Reference Pre-read Cycle

[0105] Another scheme for circumventing or alleviating the problemsrelating to parasitic currents in non-addressed cells on active bitlines shall now be described.

[0106] For concreteness, refer to, e.g. the four-level timing diagramshown in FIG. 6. The pre-charge scheme described in the above paragraphsimplies that the active bit line has been shifted to its read cyclevalue at time point 2, and ensuing parasitic currents have beensignificantly reduced by the time the active word line is switched attime point 3. The logic state in the addressed cell is determined by thesense amplifier which records the charge flowing to the bit line duringa defined time interval that starts near the time point 3 and stopsbefore the time point 4.

[0107] Ideally, such pre-charge schemes shall enable detection of thecharge flowing in response to the shifting of the active word line attime point 3, without interference from parasitic currents through cellsat inactive word lines. In practice, the parasitic currents may die downslowly and/or have an ohmic (i.e. non-transitory) component such thatsome parasitic charge is captured by the sense amplifier. Although themagnitude of the parasitic current component flowing through eachnon-addressed cell on the active bit line may be small, the currentsfrom hundreds or thousands of non-addressed cells on the active bit linemay add up to become very significant, corrupting the readout results.

[0108] Assuming stable and predictable conditions, such a parasiticcontribution may in principle be removed by subtracting a fixed amountof charge from that recorded by the sense amplifier during the readingcycle. In many instances, however, the magnitude and variability of theparasitic contribution makes this inappropriate. Thus, in addition tothe manufacturing tolerances for the device, the fatigue and imprinthistory may vary within wide limits between different cells in the samememory device and even on the same bit line, and the parasitic currentmay depend strongly upon the device temperature at the time of read-out.In addition, the parasitic current associated with a given non-addressedcell on the active bit line may depend on which logic state it is in. Inthat case the cumulative parasitic current from all non-addressed cellson the active bit line shall depend on the set of data stored in thosecells, which defies prediction.

[0109] In order to obtain a true measure of the cumulative parasiticcurrents in connection with a given read-out event, one may implement apre-read reference cycle as exemplified in FIG. 14.

[0110] The pre-read cycle immediately precedes the read-out cycle anddiffers from the latter in only one respect, namely that the active wordline is not shifted at all. The sense amplifier is activated inprecisely, the same time slot relative to the bit line voltage shifts asis the case in the subsequent read cycle. Thus, the cumulative chargedetected during the pre-read cycle shall correspond very closely to theparasitic current contributions captured during the read cycle,including contributions from the active cell. The detected charge fromthe pre-read cycle is stored and subtracted from that recorded duringthe read cycle, yielding the desired net charge from the switching ornon-switching transient in the active cell.

[0111] Clearly, the effects of fatigue, imprint, temperature and logicstates are automatically taken care of by this referencing scheme. Animportant prerequisite is that the pre-read cycle must not materiallyalter the parasitic current levels in the read cycle. Thus, the delaybetween time points P6 and 0 (cf. FIG. 14) must be sufficient forpre-read cycle transients to die down. In certain cases, two or moresuccessive pre-read cycles may be employed to obtain a reproducibleparasitic current response prior to the read cycle. However, thisincreases complexity and total readout time.

[0112] Inspection of FIG. 14 in conjunction with the four level pulseprotocol shown in FIG. 6 shows how the pre-read reference cycleprinciple may be implemented for the other pulse protocols covered bythe present invention, by trivial extension of the example given in thepresent instance.

EXAMPLE 6 Switching Protocols Involving Offset Voltages

[0113] Yet another scheme for circumventing or alleviating the problemsrelating to parasitic currents in non-addressed cells on active bitlines shall now be described.

[0114] According to Equation (2) above, the minimum disturbing voltageon non-addressed cells is V_(S)/3 (cf. Equation (3)) and the preferredembodiments described in conjunction with the four- and five-levelswitching protocols were shown to achieve this. As will be discussedbelow, it may in certain instances be preferable to deviate somewhatfrom this criterion.

[0115] Given that the memory cells exhibit certain characteristicsregarding their electrical impedance and switching properties, it ispossible to achieve a low parasitic current load on the bit line duringread operations, while at the same time keeping disturbance of thenon-addressed cells at a low level:

[0116] It is assumed that the selected cell is subjected to a voltageV_(i)=V_(S) during the period when the memory material in the cellundergoes polarization switching. Thus,

V _(S) =V _(ii) +V _(iii) −V _(iv).  (5)

[0117] It is desired to lower the cumulative leakage current on theactive bit line which flows through the non-addressed cells on thatline. This can be achieved by lowering the voltage across thenon-addressed cells by an amount 6. Thus,

V_(iii)→V_(iii)−δ.  (6)

[0118] According to (5), this increment must be compensated by acorresponding adjustment in the voltages across the remainingnon-addressed cells:

V_(ii)−V_(iv)→V_(ii)−V_(iv)+δ.  (7)

[0119] In a large matrix, the number of cells with inactive word andinactive bit lines (V_(iv)) greatly outnumber the cells with an activeword line crossing an inactive bit line (V_(ii)). To minimize theoverall disturbance of non-addressed cells in the matrix, one maytherefore impose the requirement that V_(iv) shall not be changed tocompensate for the reduction in V_(iii), in which case one has:

V_(ii)→V_(ii)+δ.  (8)

[0120] Of course, this is not the only possible choice, but it shall beassumed hereafter to facilitate understanding of the basic principlesinvolved.

[0121] Thus the V_(S)/3 protocol would be modified such that:V_(i)=V_(S), V_(ii)=V_(S)/3+δ, V_(iii)=V_(S)/3−δ, V_(iv)=−V_(S)/3. Thiscan be achieved by, e.g. leaving the potentials on the active word andbit lines unchanged, while adding δ to all inactive word and bit lines:

[0122] i) V_(i)=V_(S)=Φ_(activeBL)−Φ_(activeWL): Active word linecrossing active bit line (the selected cell)

[0123] ii) V_(ii)=V_(S)/3+δ=(Φ_(inactiveBL)+δ)−Φ_(activeWL): Active wordline crossing inactive bit line,

[0124] iii) V_(iii)=V_(S)/3−δ=Φ_(activeBL)−(Φ_(inactiveWL)+δ): Inactiveword line crossing active bit line,

[0125] iv) V_(iv)=−V_(S)/3=(Φ_(inactiveBL)+δ)−(Φ_(inactiveWL)+δ):Inactive word line crossing inactive bit line.

[0126] The magnitude of δ must be selected with due consideration to twoconflicting requirements: On the one hand, it should be as large aspossible in order to minimize parasitic current contributions to theactive bit line. On the other hand, it should be as small as possible inorder to minimize the disturbance of non-addressed cells. In practice, adecision must be made based on the specific conditions prevailing ineach case.

[0127] Furthermore it is well-known to persons skilled in the art thatthe electrically polarizable materials used as the storage or memorymedium in displays and memories can have a non-linear voltage-currentresponse characteristic which may be exploited with advantage whenimplementing switching protocols involving offset voltages. Suchnon-linear response characteristic may however, also be dependent on thespecific material and its treatment and factors which in the presentcontext may depend on the pulsing protocol parameters actually used aswell as design and scale factors. This implies that it will beimpossible to generalize about a beneficial exploitation of non-linearvoltage-current response in non-addressed cells, but that any specificembodiment involving this kind of response must be subject to theheuristics as applicable in each case. However, any heuristics of thiskind shall be considered to lie outside the scope of the presentapplication.

EXAMPLE 7 Full Row Readout

[0128] An alternative route to reducing or eliminating the spuriouscurrent contributions from non-addressed cells along active bit linesduring readout is illustrated in FIG. 15. All word lines except theactive one are clamped at a potential close to that at the senseamplifier input (defined as zero in FIG. 15). For readout of data, theactive word line is brought to the potential V_(READ), which causescurrents to flow through the cells on the crossing bit lines. Themagnitudes of the currents depend on the polarization state in each celland are determined by the sense amplifiers, one for each bit line asshown.

[0129] This scheme provides several advantages:

[0130] Voltages across all non-addressed cells are very close to zero,eliminating leakage currents that may otherwise corrupt the readout fromthe addressed cells.

[0131] The readout voltage V_(READ) may be chosen much higher than thecoercive voltage without incurring partial switching in non-addressedcells. This allows for film switching speeds approaching the intrinsicswitching speed of the polarizable material in the cells.

[0132] The scheme is compatible with large matrix arrays.

[0133] The high degree of parallelism makes possible a large datareadout rate.

[0134] Since the readout is destructive, it shall in many cases benecessary to write data back into the memory device. This can beachieved by one of the pulsing schemes described in the previousparagraphs. A different set of cells in the memory device from thosethat were read may be chosen for refresh, e.g. in conjunction withcaching.

[0135] Possible disadvantages of this scheme are largely related to theincreased demands on the circuitry performing the driving and sensingfunctions. Thus, the simultaneous switching of all cells on a long wordline shall cause a large current surge on that line (implies a need forlow source impedance in the driver stage and low impedance currentpaths. Also potential for cross-talk within the device). Furthermore, inorder to avoid loss of data a separate sense amplifier is needed on eachbit line. With the highest possible density of cells in the passivematrix, this poses a crowding problem at the edge of the matrix wherethe sense amplifiers are connected.

[0136] The switching protocols described above make possible thecontrolled switching of polarization direction of any given cell in apassive matrix arrangement, without subjecting non-addressed cells todisturbing voltages that exceed ≈V_(S)/3.

[0137] As described in the examples above, the pulsing protocols aredirectly applicable to the reading of logic states in memory cells thateither experience no polarization switching during the read cycle,defined as being in e.g. a logic “0”, or switch the direction of thepolarization, correspondingly defined as being in a logic “1”.Initialization of the memory could involve the writing of 0's in allcells, which in the case above would imply performing a read pulse cycle(destructive read). Writing would then be achieved by applying the pulsesequence for changing the polarization in those cells that shall store alogical “1” while leaving the rest of the cells unchanged. Subsequentreading of data from the memory would then require a refresh cycle to beimplemented in those cases where it is desired to retain data in thememory following the destructive read. The refresh protocol wouldrequire a complete read/refresh pulse sequence in cases where othercells are used for renewed storage than those that were readdestructively to provide the data. On the other hand, if the same cellsare used, those cells that were read as logic “0” can be left unchangedand only those that contained a “1” need to be exposed to polarizationswitching.

1. A method of driving a passive matrix addressed display or memoryarray of cells comprising an electrically polarizable materialexhibiting hysteresis, in particular a ferroelectric material, whereinthe polarization state of individual, separately selectable cells can beswitched to a desired condition by application of electric potentials orvoltages to word and bit lines in said matrix, and wherein the method ischaracterized by controlling individually a potential on selected wordand bit lines to approach or coincide with one of n predefined potentiallevels, where n≧3, the potentials on said selected word and bit linesforming subsets of said n potentials involving n_(WORD) and n_(BIT)potentials, respectively; controlling the potentials on all word- andbit lines in a time-coordinated fashion according to a protocol ortiming sequence, whereby word lines are latched in a predeterminedsequence to potentials selected among the n_(WORD) potentials, while bitlines are either latched in a predetermined sequence to potentialsselected among the n_(BIT) potentials or they are during a certainperiod of the timing sequence connected to circuitry that senses thecharges flowing between the bit line(s) and the cells connecting to saidbit line(s); and arranging said timing sequence to encompass at leasttwo distinct parts, including a “read cycle” during which chargesflowing between said selected bit line(s) and the cells connecting tosaid bit line(s) are sensed, and a “refresh/write cycle” during whichpolarization state(s) in cells connecting with selected word- and bitlines are brought to correspond with a set of predetermined values.
 2. Amethod according to claim 1, characterized by allowing one or more bitlines to float in response to charges flowing between the bit line andthe cells connecting to said bit line during said read cycle, andclamping all voltages on the word and bit lines during the refresh/writecycle.
 3. A method according to claim 1, characterized by selecting thevalues n=3 and n_(WORD)=3 and n_(BIT)=3, in case the voltages acrossnon-addressed cells do not significantly exceed V_(S)/2, where V_(S) isthe voltage across the addressed cell during read, refresh and writecycles.
 4. A method according to claim 1, characterized by selecting thevalues n=4 and N_(WORD)=4 and n_(BIT)=4, in case the voltages acrossnon-addressed cells do not significantly exceed V_(S)/3, where V_(S) isthe voltage across the addressed cell during read, refresh and writecycles.
 5. A method according to claim 1, characterized by selecting thevalues n=5 and n_(WORD)=3 and n_(BIT)=3, in case the voltages acrossnon-addressed cells do not significantly exceed V_(S)/3, where V_(S) isthe voltage across the addressed cell during read, refresh and writecycles.
 6. A method according to claim 1, characterized by subjectingnon-addressed cells along an active word line and along active bitline(s) to a maximum voltage during the read/write cycle that deviatesby a controlled value from the exact values V_(S)/2 or V_(S)/3.
 7. Amethod according to claim 6, characterized by subjecting non-addressedcells along an active word line to a voltage of a magnitude that exceedsthe exact values V_(S)/2 or V_(S)/3 by a controlled voltage increment,and at the same time subjecting non-addressed cells along selectedactive bit lines to a voltage of a magnitude that is less than the exactvalues V_(S)/2 or V_(S)/3 by a controlled voltage decrement.
 8. A methodaccording to claim 8, characterized by the controlled voltage incrementand voltage decrement being equal to each other.
 9. A method accordingto claim 1, characterized by adding a controlled voltage increment δ1 tothe potentials Φ_(inactive)WL of inactive word lines and adding acontrolled voltage increment 52 to the potentials Φ_(inactive)BL ofinactive bit lines, where δ1=δ2=0 corresponds to the read/writeprotocols with maximum V_(S)/2 or V_(S)/3 voltage exposure onnon-selected cells.
 10. A method according to claim 9, characterized byδ₁=δ₂≠0.
 11. A method according to claim 1, characterized by controllinga quiescent potential (the potential imposed on the word and bit linesduring the time between each time the read/refresh/write cycle protocolis employed) to have the same value on all word- and bit lines, i.e. azero voltage is imposed on all cells.
 12. A method according to claim 1,characterized by selecting quiescent potentials on one or more of theword- and bit lines among one of the following: a) System ground, b)Addressed word line at initiation of pulsing protocol, c) Addressed bitline at initiation of pulsing protocol, d) Power supply voltage(V_(CC)).
 13. A method according to claim 1, characterized by selectingthe potential on the selected bit line(s) in a quiescent state such thatit differs from that at the onset of a floating period (read cycle), andby said potential being brought from a quiescent value to that at theonset of the floating period, where it is clamped for a period of timecomparable to or exceeding a time constant for charging the bit line(“pre-charge pulse”).
 14. A method according to claim 1, characterizedby preceding the read cycle with a voltage shift on inactive word lines,whereby the non-addressed cells on an active bit line are subjected to avoltage bias equal to that occurring due to the active bit line voltageshift during the read cycle, said voltage shift on the inactive wordlines starting at a selected time preceding said voltage shift on theactive bit line, and terminating at the time when the latter voltageshift is initiated, in such a way that a perceived voltage bias on saidnon-addressed cells on the active bit line is continuously applied fromthe time of initiation of said voltage shift on the inactive word linesand up to the time of termination of said voltage shift on the activebit lines (“pre-charge pulse”).
 15. A method according to claim 1,characterized by applying a pre-read reference cycle which precedes theread cycle and is separated from it by a selected time, and which mimicsprecisely the pulse protocol and current detection of said read cycle,with the exception that no voltage shift is imposed on an active wordline during said pre-read reference cycle, and by employing a signalrecorded during said pre-read reference cycle as input data to thecircuitry that determines the logic state of the addressed cell.
 16. Amethod according to claim 15, characterized by said signal recordedduring the pre-read cycle being subtracted from a signal recorded duringthe read cycle.